Lithography-grade tungsten-copper substrates for wafer level packaging

摘要

Wafer-level packaging can result in significant yield improvement, cost savings, and other improvements in function. For power devices, mismatch between coefficients of thermal expansion (CTE's) between the device and the mounting substrate or package can induce stress that reduces reliability. Adapting CTE-matched composite materials to wafer-level packaging schemes would be beneficial. We describe processes and show data for tungsten-copper substrates that meet wafer specifications for form and finish.