A novel Digital DLL and its implement on the FPGA

摘要

This paper presents a novel Digital Delay-Locked Loop architecture based on clock generator and digital delay lines. Compared with other existing architectures, this one is relatively simple and need fewer components with a wider input frequency lock range and faster locking time. Furthermore, this DLL can offer an output clock which frequency is as four times as the input one, and it can change its output duty more easily. For its good low frequency locked characters and its describability by HDL (Hardware Describe Language), this DLL can be a good complement for other architectures and can be easily embedded into digital IC or implemented by any programmable devices.