The routing of large pin-count and dense BGAs has a significant impact on the cost of the PCB, primarily in terms of layer count and via technology. This paper is the result of considerable research done with the intent of providing a general flow solution to the BGA breakout problem. It explores the need for collaboration between chip, package and PCB designers -emphasizing the dependencies that need to be managed to reduce board costs. The number of variables confronted in large BGA routing is significant and this paper reveals solutions based on a logical analysis of ASIC and FPGA BGA pin density, array patterns, packaging requirements, pin swap constraints, layers, via technology, topology planning and routing methods.
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