Planar microvoids have been observed on second level interconnections between solder metallizations and copper lands on PCB boards with immersion silver surface finish. These planar microvoids differ in size and density from the more common process voids that are found in solder joints. However, unlike the process voids, these planar microvoids reduce the reliability margin by accelerating crack propagation during thermal cycling. Therefore, desired target limits on the density of microvoids of different sizes are established. Monitoring of microvoids observed during PCB assembly production correlates the occurrence of microvoids to "caves" found in the copper land underneath the immersion silver coating on the bare PCBs of the same production lots. A mechanism is proposed to explain how the caves lead to microvoids during the reflow process. While a thick silver coating and a rough copper substrate were attributed as probable causes for microvoids in a previous study, a DOE is conducted in this study using a commercial immersion silver process, to evaluate these two factors together with silver bath chemistry and PCB substrate. There are no caves found in any of the conditions in the DOE, even for an extremely thick silver coating (more than 3 microns). Although the thick silver tends to have a slightly higher microvoid density, it is still well below the desired target limits, indicating the occurrence of microvoids is also chemistry dependent.
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