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Hardware/Software Based Hierarchical Self Test for SoCs

机译:基于硬件/软件的SOC的分层自检

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Systems on a Chip (SoCs) typically consist of several processor devices, embedded memory blocks, application-specific logic blocks and complex interconnects. While embedded memory blocks are mostly equipped with built-in self test (BIST) capabilities, test methods for processors, logic blocks and interconnects are still topics of intensive research. Beyond production testing, SoCs in safety-critical applications also need built-in self test capabilities, which work independently from external control hardware. A HW/SW -based self test scheme can facilitate self test in the field of application making efficient use of structures for production test and can even supplement production test, e. g. for internal interconnects. The paper describes the architecture, cost and limitations.
机译:芯片(SOC)上的系统通常由若干处理器设备,嵌入式存储器块,特定于应用程序特定的逻辑块和复杂的互连组成。虽然嵌入式内存块大多配备内置自检(BIST)功能,但处理器,逻辑块和互连的测试方法仍然是密集研究的主题。除了生产测试之外,SOCS在安全关键应用中还需要内置的自检功能,它独立于外部控制硬件工作。 HW / SW基础的自检方案可以促进应用领域的自检,从而有效地利用生产测试,甚至可以补充生产测试,即G。用于内部互连。本文介绍了架构,成本和限制。

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