Analysis on Power Via Induced Quasi-quarter-wavelength Resonance to Reduce Crosstalk

摘要

With increasing IO counts to support higher bandwidth, organic packages are trending to larger body sizes approaching the realm of land grid array (LGA) pin fields which adds additional complexity with socket performance and mating force requirements. Major contributor to pin count is the significant number of ground pins which are typically used around high speed differential pairs for crosstalk isolation inside the package, and on the few millimeter-thick printed circuit boards (PCBs) via field which mirrors the component pin assignment. It is now becoming a common practice to use power pins to serve a dual purpose, that is intended to support crosstalk isolation between high speed signals and to provide power delivery to Serdes IO, helping to reduce overall pin count and subsequently limit package body size and to stay within a ball grid array (BGA) form factor. However, in such PCBs where power vias are adjacent to the signal vias, increased far-end crosstalk (FEXT) and resonance in differential insertion loss in a few GHz ranges can be measured for all differential signal pairs with adjacent power vias sharing the same power net. Using a 3D full-wave simulation model, a physical explanation for the unexpected resonance in the differential signal pairs is proposed, and it is verified using an analytical model. Considering the difficulty in changing the pin map of the IC-package, a different method to eliminate the power via induced quasi-quarter-wavelength resonance is proposed without changing the pin map of the package. By applying the proposed methods in a new PCB design, the resonance is eliminated and the FEXT is lowered.