A Novel Design Methodology That Solves Todays System-Level Analysis Challenges

摘要

Typical analog design verification systems do not include test environments in simulation, leading to greater possibilities of device failure. There is an immediate need for a system where DUT (Device Under Test), HIB (Hardware Interface Board) and ATE (Automatic Test Equipment) could be simulated in a familiar design environment seamlessly. This paper proposes a novel co-analysis methodology for top level system verification creating a single testbench where DUT and HIB are simulated concurrently before an ATE hardware tape out. Citing two practical use cases, key benefits include overall reduction in test hardware development cycle and flexibility between choosing only a functional verification and a full custom sanity.