Novel Predictable Methodology to Model A Third Party Trans Receiver for High Speed SERDES

摘要

High speed serial IOs like TBT and PCIE face several challenges with predicting trans receiver behavior. The validation eco-system includes many third party devices whose electrical models are not readily available. These uncharacterized devices are analyzed with generic models during simulation to measurement correlation, which introduces many gaps in evaluating actual silicon performance. The paper introduces a novel approach to model these third party trans receivers and enable a more accurate evaluation of silicon behavior. This unique methodology employs some key IO characterizing measurements, to significantly reduce trans receiver modelling gaps introduced during silicon correlation.