System-level simulation of a noisy phase-locked loop

摘要

This paper presents a compact model of a noisy phase-locked loop (PLL) for inclusion in a time-domain system simulation. The phase noise of the reference is modeled as a Wiener process, and the phase noise contribution of the voltage-controlled oscillator (VCO) is described as an Ornstein-Uhlenbeck process. The model is applied to phase error modeling for a 60 GHz OFDM system including correction of the common phase error. A close agreement is observed between the time-domain simulation and a frequency-domain model.