The advent of the 130nm silicon node introduced the use of copper metallization and low k dielectrics, promising faster performance, smaller chip sizes and lower power consumption. Although many companies have abandoned the use of true low k dielectrics at the 130nm node, this paper will illustrate the successful integration of package technology, design technology and silicon technology utilizing low k dielectrics. The system integration capabilities offered by 130nm and 90nm silicon technologies pose significant challenges to packaging technology. Higher signal I/O density in the package as a result of shrinking die sizes, support for high speed gigabit per second serdes, high speed single ended signal I/O, power support to core logic and the ability to support the overall power dissipation requirements of the complete design. Finally, the development of a robust package assembly process to ensure Cu-low k silicon reliability. This paper describes a co-design environment fostered between packaging engineers, circuit designers and silicon process developers, successfully overcoming the challenges of nanometer product design.
展开▼
