Fabrication Method of SOI-Based Single-Electron Transistor with in-Plane Side Gates

摘要

Single-electron transistor (SET), which operates with one or a few electrons utilizing Coulomb blockade effect and single electron tunneling effect, is a new kind of nanoelectronic device. In this paper, a silicon-based SET with in-plane side gates is fabricated on silicon-on-insulator (SOI) substrates using electron beam lithography (EBL) and inductively coupled plasma (ICP) dry etching, and its electrical characteristics is measured. The fabrication process is as follows: the 30-nm-thick superficial Si layer of the p-type, (100)-oriented SIMOX (separation by implanted oxygen) wafer is phosphorus doped by ion implantation and rapidly annealed for electrical activation. The SET structure with Coulomb island weakly in connection with source and drain regions and with in-plane side gates near the island is patterned using SAL601 negative resist under EBL. The resist pattern is transferred to the superficial Si film by ICP etching with CHF_3 gas. The constrictions between the island and the source and drain serve as the tunneling barriers. Then a 50-nm-thick SiO_2 film is deposited by PECVD to fill the clearance between the island and the source, drain and gates. Finally the SiO_2 on source, drain, gates region is removed using photolithography and wet etching. The source, drain, gate electrodes are formed by evaporation of Al, stripping and annealing. Carefully controlled the structure, the SET with a 70-nm-radius Coulomb island is successfully fabricated. When the temperature decreases from the room temperature to 20 K, the resistance between source and drain, R_(ds), increases from several MΩ to several GΩ. The Coulomb staircases in the source-drain current (I_(ds)) from the I_(ds)-V_(ds) characteristics and the differential conductance (dI_(ds)/dV_(ds)) oscillations from the dI_(ds)/dV_(ds)-V_(ds) characteristics are clearly observed at different gate voltage (V_g) at 2 K. The good reproducibility of the Coulomb staircases in I_(ds)-V_(ds) curve is observed. This kind of silicon-based SET has the advantages of simplicity, IC-orientation and compatibility with traditional CMOS process.