Charge trapping in ultra-thin oxynitride gate dielectrics was investigated. Relatively low bias conditions were applied to either metal-oxide-semiconductor (MOS) capacitors or transistors, while the change in charge was monitored using capacitance-voltage measurements. Under positive bias, little change in the charge found within the gate dielectric was noted while substantial change being seen under negative bias. A model is presented that is based on published work on slow states found in SiO_2. The charge trapping model is based on a singly energetic, spatially uniform distribution of defects that communicate with the silicon substrate via tunneling. The model, while fitting the data well, appears to be limited in its detailed description of the trapping properties under all bias conditions. It was found that for low bias conditions, only one type of defect is apparent. At higher negative voltages, 2 or possibly more distinct defects are observed.
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