A number of techniques are used today for resolution enhancement of critical features in leading edge lithography. One of the knobs employed in modern resolution enhancement techniques (referred to as RETs) is the use of sub-resolution assist features (SRAFs). These changes to the layout pattern result in a substantial increase in the number of polygons, and hence data sizes, as well as a corresponding increase in the complexity of mask manufacturing and mask turn around times. The existing methods of validating a certain RET on a given technology or layer mainly involves printing the reticle containing the intended RET on a wafer with the appropriate substrate for the desired layer. The engineers then proceed to take a series of SEM measurements of printed (resist) or etched test features to demonstrate the efficacy and performance of the RET over the desired process window. However, current methods do not rigorously validate the necessity of using a particular RET using electrical device performance. Judgments about the effectiveness of an RET are made based solely upon results of SEM measurements of wafer level structures. Consequently, the systematic and random metrology errors inherent in wafer level top-down SEM measurements become more significant as feature sizes shrink and tolerances become tighter. This erodes the accuracy of this technique for validating RETs. To overcome these problems, we have designed an electrical test vehicle which targets those geometries most prevalent in the cells for a given technology. Electrical test (E-test) structures are then varied around these geometries covering the design space allowed in the design rules. This method reconciles the accuracy or effectiveness of RET models using electrical device parameters and uses the same to choose the RET which results in the lowest NRE (Non-recurring expenses), while at the same time meeting all electrical requirements.
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