Deterministic Test Generation for Digital Circuits by Cellular Automata in a Java Applet

摘要

The paper presents implementation of a test pattern generation algorithm that uses cellular automata or cellular automata with bit flipping to generate a pre-computed test set. The algorithm is realized as a Java applet for automatic synthesis of the built-in self-test structure into a digital circuit modeled in VHDL using only its VHDL entity. This software tool is available on the Internet.