Characterization of Latch-Up in CMOS Inverters in Pulsed Electromagnetic Interference Environments

摘要

Latch-up effects in cascaded CMOS inverters due to pulsed electromagnetic interference (PEMI) from high power microwave sources, is reported. The cascaded inverters were designed and fabricated consisting of two identical inverters with a width to length ratio (W/L) of 3.2μm/1.6μm for n MOSFETs and 9.6μm/1.6μm for p MOSFETs.