Temperature Dependant Characteristics of Scaled NMOS Transistors with Ultra-thin High-K Dielectrics and Metal Gate Electrodes

摘要

In order to maintain the continuous scaling of CMOS devices, high-K dielectrics and metal gate electrodes have been used at ITRS 45nm technology node. In this paper, we discuss the temperature dependence of the threshold voltage, electron mobility and gate leakage current for the scaled NMOS transistor, which has an interfacial SiO{sub}2 layer (0.5nm) and an ALD (Atomic Layer Deposition) fabricated HfO{sub}2 dielectric layer (2.0nm) with a 10nm TiN metal gate electrode covered by polysilicon (Fig. 1).