Electrolytic plating of copper for emerging computer chip interconnect technologies: key challenges opportunities

摘要

As submicron interconnect chip technology evolves from the current aluminum-based deposition methods to copper-based technology, electrolytic plating of high-definition architectural structures is emerging as the leading candidate for depositing copper for deep sub-micron multi-level interconnects. With advances in photolithographic methods and the demand for increased levels of integration, thin film circuit designers are requiring the capability to fill trenches with aspect ratios of up to 7:1 and feature sizes migrating down to 0.15 micron. This study investigated the potential for consistently plating void-free copper onto patterned silicon wafers, given the requirements outlined. In conjunction with this study, it was proposed to investigate the ability to plate such structures using additive-free copper chemistry, constant current rectification and non-rotating cathode technology. Commonly held beliefs in the plating community tended toward the understanding that chemical additives and rotating cathode methods were one of the only viable methods to meet the demands of this process.