In this paper, the process induced residual stresses in the Plastic Ball Grid Array (PBGA) packages were investigated. A typical structure in a PBGA package consists of four layers: plastic molding compound, a silicon chip, a chip attach adhesive layer and an organic chip-carrier. Due to the coefficient of thermal expansion (CTE) mismatch between the silicon chip, the plastic compound and the organic chip carrier, considerable residual stresses are developed in the package during the assembly process. Moire interferometry was used in conjunction with hole-drilling method to determine the residual stresses in different layers of the packages. A small hole was drilled at the plastic side and the chip carrier side, respectively. The relationship between the released surface displacements and the corresponding residual stress was established by introducing a set of calibration coefficients. A multilayer 3D-FEM model was established to determine the relevant calibration coefficients. For a practical PBGA package, the tensile residual stresses were determined in both the plastic molding compound and the glass/epoxy laminate chip carrier, whereas compressive residual stress was found in the silicon chip. The method is accurate, simple, convenient and practical. More applications in electronic products are anticipated.
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