DRAM Technology Challenges

摘要

(1) limits in device scaling require new cell concepts (Vertical Transistor Cell) at <100nm (2) new cell concepts offer potential for smaller cell size (3) constant cell capacitance requires new materials for node dielectric ≤70nm (4) process challenges (STI, Gate Stack, Collar, CB contact,...) need engineering effort (5) efforts for reduction of manufacturing costs underway (300mm, ...., APC) (6) DRAM scaling will continue for the next upcoming generations