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Addressing Prolonged Restore Challenges in Further Scaling Drams

机译:解决进一步扩展Dram的长期恢复挑战

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摘要

As the de facto memory technology, DRAM has enjoyed continuous scaling over the past decades to keep performance growth and capacity enhancement. However, DRAM further scaling into deep sub-micron regime faces significant challenges. Among the induced issues, prolonged restore time is expected to be one of the major concerns, but it has been paid little attention. Aiming at restore issue, this thesis performs pioneering studies to characterize the problems, and presents techniques from different perspectives to overcome them.;First, our experimental studies quantify the significant restore process variations, caus- ing serious degradations on yield and/or performance. To solve the problem, we propose schemes to expose the variations to the architectural levels. Fast restore chunks can thus be constructed utilizing DRAM organization, and they can be exposed to the memory controller to effectively compensate the performance loss. Further, we maximize the improvement by applying restore-time-aware rank construction and hotness-aware page allocation schemes to fully utilize the fast regions.;Second, in addition to simply expose the variations to higher levels, we investigate DRAM cell structures and behaviors finding that refresh and restore are two strongly correlated operations. Whereas are being fully restored after each read or write access, DRAM cells are always being fully charged by periodical refresh operations, providing an opportunity to early terminate restore. With the insight, we first propose to truncate a restore using the time distance to next refresh. Further, to provide more truncation opportunities, we integrate the multirate-refresh concepts to shorten the distance by increasing the refresh rate of recently accessed regions.;Lastly, we explore higher to the application level with the inspiration that a large set of applications can well tolerate output accuracy loss and runtime errors, enabling us to exploit approximate computing to mitigate prolonged restore. By utilizing the variance in restore timing exhibited at different row segments, we reduce the restore time such that only partial segments are fully reliable. We then map the critical data onto the reliable segments to keep the application-level errors low. Atop of the approximation-aware technique, we further generalize it to support precise computing as well.
机译:作为事实上的存储技术,DRAM在过去几十年中一直在不断扩展,以保持性能增长和容量增强。然而,DRAM进一步扩展到深亚微米体系面临巨大挑战。在引起的问题中,延长恢复时间预计将是主要问题之一,但很少引起注意。针对还原问题,本文进行了开创性的研究来表征问题,并从不同的角度提出了克服这些问题的技术。首先,我们的实验研究量化了重大的还原过程变化,从而导致产量和/或性能的严重下降。为了解决该问题,我们提出了一些方案来将变化暴露到体系结构级别。因此,可以使用DRAM组织来构建快速恢复块,并且可以将其暴露给内存控制器以有效补偿性能损失。此外,我们通过应用感知还原时间的等级构造和感知热点的页面分配方案来充分利用快速区域,从而最大程度地提高了性能。第二,除了简单地将变化暴露在更高的层次之外,我们还研究了DRAM单元的结构和行为。发现刷新和还原是两个高度相关的操作。每次读取或写入访问后都将完全恢复,而DRAM单元始终通过定期刷新操作充满电,从而提供了提前终止恢复的机会。有了见识,我们首先建议使用到下次刷新的时间距离来截断还原。此外,为了提供更多的截断机会,我们集成了多速率刷新概念,通过增加最近访问的区域的刷新率来缩短距离。最后,我们在更高的应用程序级别上进行了探索,并获得了很多应用程序都可以很好地解决的启发。容忍输出精度损失和运行时错误,使我们能够利用近似计算来减轻长时间的恢复。通过利用在不同行段上显示的恢复时序的差异,我们减少了恢复时间,从而只有部分段是完全可靠的。然后,我们将关键数据映射到可靠的段上,以保持较低的应用程序级错误。除了近似感知技术之外,我们还进一步推广了该技术以支持精确计算。

著录项

  • 作者

    Zhang, Xianwei.;

  • 作者单位

    University of Pittsburgh.;

  • 授予单位 University of Pittsburgh.;
  • 学科 Computer science.;Computer engineering.;Electrical engineering.
  • 学位 Ph.D.
  • 年度 2017
  • 页码 134 p.
  • 总页数 134
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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