Comparisons in L32 2k-Factorial and L25 Taguchi for the 16 nm FinFET Statistical Optimization Applications

摘要

This project examines and analyzes the process parameter variance towards on-state drive current (I_(ON)) and leakage current (I_(OFF)) towards the 16 nm double-gate FinFET (DG-FinFET) device by the implementation of 2k-factorial design, with comparisons made against an L_(25) Taguchi statistical method. Alterations with two levels for six process parameters consisting of the threshold voltage (V_(TH)) doping dose, V_(TH) doping tilt, polysilicon doping dose, polysilicon doping tilt, Source and Drain (S/D) doping dose and S/D doping tilt will be done to analyze and improve the results of both I_(ON) and I_(OFF). The physical characteristics of the device will be defined on the ATHENA module, with the ATLAS module then used to characterize its electrical properties. Consideration is made with the responses from both modules by the assistance of the L32 2κ-factorial design to reduce the device's variability as well as maximizing the value of I_(ON) while minimizing the I_(OFF) value. By achieving both values, the I_(ON)/I_(OFF) ratio are able to be maximized in order to reduce the power consumption of the device subsequently. The most dominant factor towards both I_(ON) and I_(OFF) values is identified with polysilicon doping tilt, showcasing the largest standardized effects at the end of this experiment. The optimum values achieved with 2κ-factorial design with I_(ON) and I_(OFF) at 1648.48 μA/μm and 42.096 pA/μm respectively while achieving better I_(ON)/I_(OFF) ratio with 39.160 × 10~6 as its I_(ON) have surpassed the value of I_(ON) achieved in Taguchi method that was valued at 1559.96 μA/μm. Importantly, the results acquired have met the predictions of the International Technology Roadmap Semiconductor (ITRS) 2013 for the year 2020.