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Process design of superjunction MOSFETs for high drain current capability and low on-resistance

机译:高漏电流能力和低导通电流仪的超结MOSFET的工艺设计

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This paper reports that the process design to cope with both high drain current density and low on-resistance in the superjunction (SJ) MOSFET. The SJ structure is attractive to reduce the specific on-resistance dramatically due to the charge compensation concept. The drain saturation current density, however, is limited by JFET depletion at bottom region of the SJ structure. This is an obstacle to shrink the chip area due to low drain current capability, even if the on-resistance can be reduced by the lateral SJ pitch narrowing. Since the SJ structure depletion is determined by the column active doping density, the SJ process design strongly affects the saturation current density and the on-resistance. The process margin cut and high doping efficiency are key factors for the compatibility between the increase of saturation drain current density and the on-resistance reduction in SJ-MOSFET.
机译:本文报道了过程设计,以应对高漏极电流密度和超结电流的低导通电阻(SJ)MOSFET。由于电荷补偿概念,SJ结构具有吸引力地降低了特定的导通电阻。然而,排水饱和电流密度受到SJ结构底部区域的JFET耗尽的限制。即使通过横向SJ间距变窄可以减小导通电阻,这是由于低漏电流能力而缩小芯片区域的障碍。由于SJ结构耗竭由柱主动掺杂密度确定,因此SJ工艺设计强烈影响饱和电流密度和导通电阻。过程边缘切割和高掺杂效率是饱和漏极电流密度的增加与SJ-MOSFET的导通电阻之间的兼容性的关键因素。

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