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Low on-resistance 4H-SiC UMOSFET with local floating superjunction

机译:具有局部浮动超结的低导通电阻4H-SiC UMOSFET

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This paper introduces an improved on-resistance 4H-SiC UMOSFET structure. Compared to conventional p-shielding UMOSFETs, the proposed 4H-SiC UMOSFET with a local floating superjunction (LFS) exhibits lower on-resistance while maintaining a breakdown voltage of 1700 V. The structure has a superjunction located beneath the p-shielding. It was optimized for various parameters to reduce the on-resistance while maintaining the breakdown voltage. The on-resistances of a conventional UMOSFET and the optimized LFS-UMOSFET are 13.75 and 8.68 m Omega cm(2), respectively, when the gate voltage is 10 V. The proposed UMOSFET showed a 36.8% reduction in the specific on-resistance, the figure of merit was improved by 35.1%, and the maximum current density was improved by 29%. Also body diode characteristic and UIS test are confirmed. All the results are demonstrated by Sentaurus TCAD simulation.
机译:本文介绍了一种改进的导通电阻4H-SiC UMOSFET结构。与传统的p屏蔽UMOSFET相比,拟议的具有局部浮动超结(LFS)的4H-SiC UMOSFET在保持1700 V击穿电压的同时,具有较低的导通电阻。该结构的超结位于p屏蔽下方。针对各种参数进行了优化,以降低导通电阻,同时保持击穿电压。当栅极电压为10 V时,常规UMOSFET和优化的LFS-UMOSFET的导通电阻分别为13.75和8.68 m Omega cm(2)。建议的UMOSFET的比导通电阻降低了36.8%,品质因数提高了35.1%,最大电流密度提高了29%。体二极管的特性和UIS测试也得到了确认。所有结果都通过Sentaurus TCAD仿真得到证明。

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