From system design to clock skew impact study in parallel sigma delta modulators using frequency band decomposition

摘要

This paper presents the study of a novel parallel architecture of analog-to-digital converters (ADCs) based on sigma delta (ΣΔ) modulators using frequency band decomposition (FBD). This architecture is intended for wideband applications with a fractional bandwidth equal to 40% and composed of four channels of 6th order band-pass discrete time (DT) ΣΔ modulators with single-bit quantization. The simulation results prove that this architecture is able to provide a signal-to-noise ratio (SNR) over 50 dB. These results satisfy the wideband standard requirements. However, parallel architectures are sensitive to channel mismatches. In this paper, we are interested in studying the robustness of our FBD architecture to clock skew mismatch errors. It is shown that the clock skew causes the SNR to decrease by at most 6 dB.