Challenges for the quality control of assist features for 45nm nodetechnology and beyond

摘要

Current flash memory technology is facing more and more challenges for 45nm and 32nm node technology. To get goodCD and yield control, optimized RET, OPC modeling and DFM techniques have to be applied [1]. To enhance processwindow (PW) and better CD control for main features, assist features (SB) have to be used. Simulation and waferevaluation show that the SB CD performance is very critical. Based on OPC simulation, we can get a very goodprediction about the CD size and placement of assist features. However, we can not always get what we want from masksuppliers. For 45nm node technology and beyond, The SB CD size (– 20nm at 1X) has almost pushed to the currentmask process limit. Wafer fabs have a very big concern about the stability of linearity signatures from differentsuppliers and different products in order to keep high accuracy of OPC models. Actually the CD linearity signaturevaries from one mask supplier to another and also varies from product to product. To improve the SB CD control, theideal goal is to make "flat" linearity for all mask suppliers. By working closely with TPI mask supplier, we come upsolutions to improve SB CD control to get "flat" linearity. Also technology development is causing more severe SBprintability, we proposed a methodology to use AIMS for predicting SB printability. Wafer results proved the feasibilityfor these methodologies.