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An ultra-low power consumption 1-V, 10-bit succesive approximation ADC

机译:超低功耗1-V,10位成功近似ADC

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An ultra-low power consumption 10-bit rail-to-rail input range succesive-approximation Analog-to-Digital Converter (ADC) for sensor network applications is presented. It is designed in a standard 0.13μm CMOS process technology. The converter consists of a capacitor-based digital-to-analog converter, a two-stage voltage comparator, formed by a pre-amplifier and a dynamic-latch, a passive sample-and-hold circuit, a current reference generator and digital circuitry for switching and control. Post-layout simulations show that the ADC consumes less than 2μW at a conversion rate of 100kS/s from a 1V voltage supply. Proper operation is achieved down to a supply voltage of 0.8 V.
机译:提供了用于传感器网络应用的超低功耗10位轨到轨输入范围成功逼近模数转换器(ADC)。它以标准的0.13μmCMOS工艺技术设计。转换器由基于电容的数字 - 模拟转换器,双级电压比较器,由预放大器和动态锁存器,无源样本和保持电路,电流参考发生器和数字电路形成的两级电压比较器。用于切换和控制。后布局模拟表明,ADC以100V电压电源的100KS / S的转换速率消耗小于2μW。正确的操作实现为0.8V的电源电压。

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