256×256-bit multiplier using multi-granular embedded DSP blocks in FPGAs

摘要

This paper proposes an efficient design methodology for implementing a large-size signed multiplier using multi-granular embedded blocks. A 256×256-bit 2's complement multiplier is implemented based on 18×18-bit and 36×36-bit embedded multipliers. The use of the multiple-size embedded blocks with a new sign-extension scheme efficiently simplifies the addition of the partial products, therefore reduces the execution delay and the required area of the multiplication. The proposed approach has been implemented and tested targeting Altera's Stratix II FPGAs with the aid of the Quartus II software tool. The experimental results have shown that this design approach is better, in terms of speed and area usage, than the standard approach used by Quartus II tool. On average, the delay reduction is about 21.77% and the area saving, in terms of ALUTs, is about 71.48%.