基于改进的布斯算法FPGA嵌入式18×18乘法器

摘要

A multiplier embedded in FPGA was designed. It can perform 18 X18-bit signed number or 17X17-bit unsigned number multiplying operation, and is based on modified Booth algorithm. In order to improve the speed of the multiplier. a new structure of Booth encoder and partial product was proposed, and 9-2 compressed tree and carry lookahead adder (CLA) were optimized. TSMC 0.18 μm CMOS technique is adopted in this multiplier. Its critical path delay is 3. 46 ns.%设计了一款嵌入FPGA的乘法器,该乘法器能够满足两个18 b有符号或17 b无符号数的乘法运算.该设计基于改进的布斯算法,提出了一种新的布斯译码和部分积结构,并对9-2压缩树和超前进位加法器进行了优化.该乘法器采用TSMC 0.18μm CMOS工艺,其关键路径延迟为3.46 ns.