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Prospects of Hf-based Gate Dielectrics by PVD with FUSI Gate for LSTP Application

机译:用于LSTP应用的PVD对HF基栅电介质的前景

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Study of Hf-based high-k gate stack prepared by PVD-Hf02 and its silicate with Ni-Fully Silicide(FUSI) gate focusing on interfacial reaction between high-k and Ni-FUSI electrode is overviewed. Effects of SiN capping between Ni-FUSI gate and high-k dielectric and post deposition anneal (PDA) to suppress the reaction during FUSI process were investigated. The SiN cap could increase transistor yield and PDA could suppress instability of the drive current due to defects/roughness caused by interfacial reaction during NiSi formation. It is noteworthy that not only elimination of poly-Si depletion but also EOT reduction was observed by replacing the poly-Si with the Ni-FUSI, which was remarkable for Ni-FUSI/SiON than Hf02 case. Hereof, by optimizing the PDA condition with SiN cap, decent electrical characteristics were obtained, lon(n/p) > 600/200 uA/um at bff = 20 pA/um at Vad = 1.1 V. This drivability meets low stand-by power specification of the MOSFET for 45 nm node.
机译:通过PVD-HF02制备的基于HF的高k浇口堆及其具有Ni-全硅化物(FUSI)栅极的硅酸盐,聚焦在高k和Ni-Fusi电极之间的界面反应上。研究了Ni-Fusi栅极和高k电介质和后沉积退火(PDA)在FUSI过程中抑制反应的影响。 SIN帽可以提高晶体管产率,并且PDA可以抑制由于NISI形成期间由界面反应引起的缺陷/粗糙度而抑制驱动电流的不稳定性。值得注意的是,不仅通过用Ni-Fusi替换Poly-Si来观察到聚-Si耗尽而且还观察到EOT减少,这对于Ni-Fusi / Sion比HF02案件显着显着。因此,通过优化具有SIN帽的PDA条件,获得了体面的电气特性,在VAD = 1.1 V的BFF = 20 PA / UM处的LON(N / P)> 600/200 UA / UM。这种驾驶性能符合低待机性MOSFET的功率规范45 nm节点。

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