HIGH-K MATERIALS IN FLASH MEMORIES

摘要

The scaling down of Flash memories can be pursued using the conventional stacked gate architecture only with major changes of the active dielectrics, mainly the inter-poly dielectric (IPD). The necessity to reduce the writing/erasing voltages keeping satisfactory value for the capacitance coupling ratio (aG) in order to guarantee an efficient voltage transfer from the control gate to the floating gate, leads to an aggressive reduction of the IPD Equivalent Oxide Thickness (EOT). Moreover, from the 45nm node, the IPD EOT should be further reduced, due to the loss of the contribution of the vertical sidewalls of the poly floating gate. The required 4-6 nm EOT thickness for the IPD cannot be achieved by the conventional ONO (Oxide-Nitride-Oxide) technology which starts failing in the 10-12 nm range in terms of charge retention properties. Therefore high-k materials are currently investigated for IPD formation in future Flash memories. It is worth noticing that the requirements for IPD are very different from those of the gate dielectrics used in logic circuits. First, in order to guarantee the charge retention specification of 10 years, the target EOT for IPD is much higher and the maximum leakage current (at high temperatures and low voltages) is much lower than the ones required for gate oxides. Second, integration issues for IPD are more severe than those for gate oxide in logic circuits, due to the exposure of the IPD stack to wet and oxidation chemistries, to the multiple dry etching steps for the definition of the structures, and to an overall thermal budget higher than the one for logic circuits and that may cause the film crystallization. Therefore, thermal stability, compatibility with several process steps, low leakage current also for crystalline films, as well as the compatibility with wet chemistries and oxidation treatments are the challenging requirements for high-k based structures in NVM. Alumina and alumina based materials (like hafnium aluminates) are among the possible candidates. Promising and tunable electrical and structural properties are achieved for these materials by varying the high-k stack chemical compositions and post-deposition thermal treatments. Proper test structures with a floating gate and different high-k oxides as IPD have been fabricated and tested electrically in order to identify the most suitable materials for integration in real memory devices. Hafnium silicates have been also evaluated and compared with hafnium aluminates and Al203. Different material combinations have been selected as potential solutions for the replacement of the conventional ONO (Oxide-Nitride-Oxide) stack.