HIGH-K MATERIALS FOR TUNNEL BARRIER ENGINEERING IN FUTURE MEMORY TECHNOLOGIES

摘要

Replacing the tunnel oxide or interpoly dielectric of a floating gate Flash memory cell by an engineered tunneling barrier allows lowering the voltage necessary to program or erase the memory cell. We use dual layer dielectric stacks with different dielectric constant, allowing a high tunneling current at relatively low applied voltage while providing good data retention. Stacks consisting of Si02 with Hf02 or Al203 have been studied in single poly memory cells, demonstrating both low voltage programming by tunneling and 10 years of data retention. These stacks have also been integrated as interpoly dielectric (IPD) in a 0.18pm HIMOSTM process for low voltage erasing by tunneling through the IPD.