Power semiconductor modules with IGBTs (insulated gate bipolar transistor) in a range from 600 V - 6500 V and up to 200 A per chip are connected with heavy wires of up to 500μm in diameter. The interconnection between Aluminum wires and semiconductor surfaces plays an important role for reliability. Due to the high thermo-mechanical stress the lifetime is limited by wire material and bonding quality. To reach a good connection and a good yield it is important to optimize the bond process and the layout. In this paper a technique is described, which allows to detect time and location of destruction during wire bonding.
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