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Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility

机译:动态指令合并和可重新配置的数组:数据流执行软件兼容性

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摘要

As Moore’s law is loosing steam, one already sees the phenomenon of clock frequency reduction caused by the excessive power dissipation. New technologies that will completely or partially replace silicon are arising, and new architectural alternatives are necessary. Reconfigurable fabric appears to be one of these solutions, and has shown speed ups of critical parts of several data stream programs. However, its wide spread use is still withhold by the need of special tools and compilers, which clearly preclude software portability. Based on all these facts, in this work we propose a coarse-grain dynamic reconfigurable array, tightly coupled to a traditional RISC machine. Besides taking advantage of using combinational logic to speed up the execution, we implement dynamic analysis of the code at run time to reconfigure the array, maintaining full software compatibility. Using the Simplescalar Toolset together with the embedded benchmark suite MIBench, we show performance improvements until 2 times, thanks to the implementation of the proposed approach.
机译:随着摩尔定律的蒸汽,人们已经看到了由过度功耗引起的时钟频率减少现象。完全或部分替代硅的新技术正在发生,并且需要新的建筑替代品。可重新配置的结构似乎是这些解决方案之一,并显示了几个数据流程序的关键部分的速度。但是,它的广泛频繁使用仍然需要特殊的工具和编译器,这清楚地妨碍了软件便携性。基于所有这些事实,在这项工作中,我们提出了一种粗晶动态可重构阵列,紧密耦合到传统的RISC机器。除了利用组合逻辑加速执行外,我们在运行时实现了对代码的动态分析,以重新配置阵列,维护完整的软件兼容性。使用简单的基准套件Mibench以及嵌入式基准套件Mibench,由于实现了所提出的方法,我们会显示性能改进,直到2次。

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