NANOELECTRONICS ON SEMICONDUCTOR/SOLUTION INTERPACES

摘要

A direct writing process of metallic nanostmctures on semiconductor/solution interfaces without lithographical intermediate steps is discussed. This "bottom-up" process is based on defined local nucleation and growth conditions on the semiconductor/solution interface determined by supersaturation or undersaturation, binding energy and crystallographic misfit between adatoms and the substrate, internal strain, etc.. Experimental results show that the nucleation and growth conditions of the metal deposition process on the elemental semiconductor substrate of n-Si(Ill):H become highly uniform and reproducible since surface lithography is avoided. Nanostmctures typically represent "low-dimensional systems (LDSs)". First results on the changed energetic and kinetic properties of metal LDSs compared to those of 3D metal phases are presented.