Approaches to monolithic wafer-level three-dimensional integrated circuits (3D ICs) generally involve bonding of processed wafers. Various bonding issues are described, focusing on the more stringent technology of back-end, monolithic, wafer-level 3D hyper-integration, aimed at forming high-performance, multifunctional nanosystems at the sub-100 nm technology node. The specific 3D technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and selective etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a dielectric bonding adhesive that provides robust wafer bonding and eases pre-bonding wafer planarization requirements is a key to process compatibility with standard IC and packaging processes. The desirable properties of dielectric bonding adhesives, bond strength and issues related to bonded functional IC layers with multilevel interconnects are discussed, and future needs of dielectric adhesive bonding are projected.
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