Heterostructure Source-Gated Transistors: Challenges in Design and Fabrication

摘要

Source-gated transistors (SGTs) are usually made with a Schottky source contact which acts as the current-control mechanism. We propose an alternative method, using an ohmic source contact and a bulk barrier. Here, we realize the bulk barrier at the source with a tri-layer C70/C60/C70 heterostructure, which should lead to improved dynamic range and reduced temperature dependence of drain current, as well as the usual energy and gain characteristics of SGTs. Measurements correlate well with Silvaco Atlas simulations and show: low hysteresis, indicating good quality interfaces; a large threshold shift due to the bulk barrier and residual charge in the heterostructure; and FET-like saturation, due to the interplay between semiconductor mobility and barrier height. We discuss the benefits of such structures, and also the fabrication and design challenges associated with this type of transistor (chemistry and materials, barrier realization, interface properties, and requirements on charge carrier mobility).