P+/N JUNCTION FORMATION IN THIN STRAIN RELAXED BUFFER STRAINED SILICON SUBSTRATES: THE EFFECT OF THE JUNCTION ANNEAL

摘要

The effect of the junction anneal on the electrical characteristics of Highly Doped Drain (HDD) junctions in silicon-germanium (SiGe) Strain Relaxed Buffers (SRB's) is examined. The SRB's in this paper use a thin C-rich layer, allowing the growth of very thin (~250nm) SRB's. Two types of SRB's have been grown, placing the C-rich layer inside or outside the junction's space charge region (SCR) at zero bias. The effect of the junction anneal on the current characteristics is in relative terms less pronounced on the SRB's than on bulk Si diodes, suggesting that a different amount of defect out-annealing takes place, when the annealing temperature is increased. A first-order estimation of the minority carrier generation lifetime confirms this trend. When the reverse voltage is increased, the C-rich layer will be contained in the SCR for all SRB's, making the quality of the junctions comparable in between the SRB's. This is confirmed by leakage current measurements at elevated temperatures.