This paper presents the results of integration of the Hf based high-k dielectrics into standard bulk CMOS process with poly-Si and Ni-FUSI gate electrodes The main high-k deposition techniques (ALD, MOCVD and PVD) are discussed. The most important results from the dry etch patterning of the poly-Si gates are presented. The issue of the high-k removal from the source and drain areas by means of combination of dry and wet etch is discussed in detail. It is shown that the transistors with poly-Si gates (especially the pMOS transistors) exhibit insufficient transistor drive current. The main reason for this is attributed to the electron and hole mobility degradation as well as to the degradation in the inversion capacitance. This is thought to be a direct consequence of the Fermi level pinning at the poly-Si / Hf based dielectric interface. The problem of the Cmv degradation is shown to be resolved by means of full Ni silicidation of the poly-Si gate electrode. Corresponding improvement in the Ioff-Ion curves is presented. Results of the Ni-FUSI gate work function modification by means of gate ion implantation are presented as well. The data shows that the more WF change is achieved when SiON gate dielectric is used in combination with Ni-FUSI gate electrode as opposed to the Hf based high-k gate dielectric. This indicates that the Fermi level pinning remains at the poly-Si/ Hf based dielectric interface and the issues of the pMOS long channel VT pertains to the Ni-FUSI / HfO2 (HfSiON) gate stacks. As a conclusion of the presented and discussed data it is stated that the Ni-FUSI / H1D2 (HfSiON) gate stacks are suitable for the Low Stand by Power applications with rather high VT requirements. Further scaling of the transistors for High Performance application will be probably enabled only by successful combination of metal gates (not Si based, like FUSI) with high-k gate dielectric.
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