SURFACE PREPARATION and CLEANING CHALLENGES FOR sub-65nm PROCESS INTEGRATION

摘要

The Semiconductor industry has shown remarkable ingenuity in breaking through virtually all of the technology barriers that have been presented as obstacles to Moore's Law scaling [1]. Many of these barriers have been overcome with major advances in process equipment. One often overlooked technology enabler has been surface preparation and wafer cleaning. Advances in surface preparation have allowed for the deposition of new materials used in gate stacks, interconnects, and DRAM storage electrodes. In addition, surface preparation developments have reduced material losses which are vital to maintaining shrinking critical dimensions (CDs) and film thicknesses. Many of the advances in surface preparation have been realized with a shift from batch processing to single wafer processing.