Cost-Effective Multirate Cascaded Integrator Comb Decimator Filter Design on Field Programmable Gate Arrays

摘要

Cascaded Integrator Comb (CIC) filters are one of the most economical multirate filters widely used as decimators in digital receivers. Size/power improvements in this crucial unit of a digital receiver may essentially improve system performance including battery lifetime of the wireless portable system. Since, the only block in this filter structure that can be improved for better size/power performance is the adder, we have designed several CIC decimators using different means of arithmetic and the designs are synthesized for Altera's Field Programmable Gate Arrays (FPGAs). The arithmetic schemes used are two's complement addition, Carry Save Adder (CSA) using parallel counter logic and the Modified Carry Save Adder (MCSA) that incorporates Wallace tree structure. Each of these CIC decimators is a 16 bit I/O bit-width, 5-stage design with a rate change factor of 1000. Due to the presence of the integrators, the internal required bit-width is 66 bits. In order to maintain the same number of input and output bit-widths, two different Pruning schemes are used, pruning done at each stage of the design and pruning at the final stage alone. Results of synthesis are tabulated for the individual adder designs and the CIC designs with both the pruning schemes for all possible synthesis options. Depending on the requirements of the application, the results of the synthesis can be used to choose a CIC decimator that consumes less silicon or a design that provides better speed or a design which is most cost effective in terms of area/speed product.