YIELD MODEL FOR ASSEMBLY OF AREA ARRAY SOLDER INTERCONNECT PACKAGES WITH EXPERIMENTAL VERIFICATION

摘要

Area array solder joints are difficult to visually inspect because solder joints are very tiny and covered by the chip. It may result in the increase of the interconnect defects passing the inspection step. Those defects become evident in later process steps or in the testing of the finished product. Since reworking of area array interconnects is very difficult and costly, interconnect yield is the crucial issue that determines the final product cost. The significance of interconnect yield becomes obvious as the demand on area array packages is growing. Therefore, it is essential to reduce the yield defects as close to zero as possible. The objective of this paper is to suggest design guidelines to implement Six Sigma, i.e., less than 3.5 defects per million in the assembly process of area array solder interconnect packages. For that purpose, the parameters impacting on interconnect yield are identified, the cause and effect relationships of design and process parameters to interconnect yield are analyzed, and the process design rules to statistically achieve Six Sigma are developed in general and explicit forms.