New Generation Wafer-level (Chip Scale) Package Technology Delivers Higher Levels of Power and Reliability Performance for Power MOSFET Devices

摘要

This paper describes a new wafer-level packaging technology which has been used for the development of a new area array flip chip scale package family called MICRO FOOT. The development of these microminiaturized packages is based on the combination of a proprietary wafer-level packaging (WLP) process and Trench-FET silicon technology. Developed as next generation chip scale (CS) packages, they are directed towards cell phones, battery packs and other handheld electronic systems. The wafer-level packaging resolves interconnection challenges associated with conventional surface-mount packaging and improves device electrical performance in portable electronics. In the WLP process we apply a new under-bump metallization (UBM) by employing a novel electroless nickel and gold plating technique. The UBM serves as a base metal for printing solder bumps to form area array interconnections for flip chip mounting. We will present two of the world's smallest single p-channel and bidirectional n-channel MICRO FOOT power MOSFETs, that offer the industry's lowest Rdson. They have been developed for Li-Ion battery pack switching and protection applications. With the achievement of a 100% silicon to footprint ratio, these two products offer ultra-low on-resistance and excellent thermal performance. Furthermore, they offer a 75% to 80% smaller footprint area than the industry-standard surface-mount TSOP-6 and TSSOP-8 devices. Finally, we will present the results of an extensive reliability program, which was supported by a 3D finite element thermo-mechanical study.