Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node

摘要

Regular fabric structure is expected to reduce the process variations and increase the yield in sub-micron technology regime. Few experimental assessments, however, for the effectiveness of the regular structures has been carried out yet. In this paper, three kinds of circuit blocks are implemented with four kinds of layout styles with different regularity, and the effect of regularity on the circuit performance variations is evaluated. A test chip is fabricated with 90nm CMOS logic process and measured results show that the regular structure increases average delay, and the worst delay of the regular structure is not better than the worst delay of normal circuits with irregular standard cells.