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TECHNICAL CHALLENGES IN MEMORY PACKAGING

机译:内存包装中的技术挑战

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Well known Moore's Law shows, number of transistors would be double in every 1.5 years. It is still accurate Jitting for logics after the quarter century history of Integrated Circuit industry, so it might be a kind of Semiconductor Bible. However, even in CMOS logic process, it is getting difficult to achieve it because of device scalability, getting larger leakage current and parasitic resistance/capacitance. In the memory processes, Memory has recently slower integration growth than ever as well as comparing with CMOS process because of complicated cell structure, consequently twofold density increase in every two years. As mentioned in this paper, memory application area get increased over the classical main memory application of computer. To provide memory density that follows Moore's Law, Fab. oriented development activity is not sufficient. Packaging technology is expected to take part in important role to increase memory growth rate. Mobile application is pretty new area that grows very fast, and requires small form factor but high density from various memory types.
机译:众所周知的Moore的法律表演,晶体管的数量每1.5年都会增加两倍。在集成电路行业的四分之一世纪历史之后,它仍然准确的逻辑逻辑,因此它可能是一种半导体圣经。然而,即使在CMOS逻辑过程中,由于设备可伸缩性,难以实现它,获得更大的漏电流和寄生电阻/电容。在内存过程中,内存最近的集成增长比以往更慢,并且由于细胞结构复杂的CMOS过程比较,因此两年两年的双重密度增加。如本文所述,内存应用区域会在计算机的经典主存储器应用上增加。提供跟随摩尔法,工厂的记忆密度。导向的发展活动不足。预计包装技术将参与重要作用,以提高内存增长率。移动应用程序非常新的区域,其生长非常快,并且需要小的外形,但来自各种内存类型的高密度。

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