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TECHNICAL CHALLENGES IN MEMORY PACKAGING

机译:内存包装中的技术挑战

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Well known Moore's Law shows, number of transistors would be double in every 1.5 years. It is still accurate Jitting for logics after the quarter century history of Integrated Circuit industry, so it might be a kind of Semiconductor Bible. However, even in CMOS logic process, it is getting difficult to achieve it because of device scalability, getting larger leakage current and parasitic resistance/capacitance. In the memory processes, Memory has recently slower integration growth than ever as well as comparing with CMOS process because of complicated cell structure, consequently twofold density increase in every two years. As mentioned in this paper, memory application area get increased over the classical main memory application of computer. To provide memory density that follows Moore's Law, Fab. oriented development activity is not sufficient. Packaging technology is expected to take part in important role to increase memory growth rate. Mobile application is pretty new area that grows very fast, and requires small form factor but high density from various memory types.
机译:众所周知的摩尔定律表明,每1.5年晶体管的数量将增加一倍。在四分之一世纪的集成电路行业历史之后,对于逻辑来说仍然是准确的“ Jitting”,因此它可能是一本《半导体圣经》。但是,即使在CMOS逻辑工艺中,由于器件的可扩展性,越来越大的泄漏电流和寄生电阻/电容,也很难实现这一目标。在存储过程中,由于单元结构复杂,近来与CMOS过程相比,Memory的集成增长比以往任何时候都要慢,因此每两年密度增加两倍。如本文所述,内存的应用领域比计算机的经典主内存应用有所增加。为了提供遵循摩尔定律(Fab)的存储密度。定向的发展活动还不够。预计封装技术将在提高内存增长率方面发挥重要作用。移动应用程序是一个非常新的领域,它增长非常快,并且要求各种内存类型的外形尺寸小但密度高。

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