MICROELECTRONICS PACKAGING RESEARCH DIRECTIONS FOR AEROSPACE APPLICATIONS

摘要

The research directions discussion begins with an assessment of needs from the microelectronics for aerospace applications viewpoint. Predictions for microelectronics are embedded within the Needs Assessment discussion. Greater functional density packaged in a smaller form factor is the most persistent challenge facing the microelectronics packaging research community. The use of COTS devices is of interest to NASA due to wide availability and cost, however the need for higher reliability and longer field life is of concern. Chip packaging has migrated from ceramic to plastic area array packages such as Ball Grid Arrays, and Chip Scale Packages. Research needs also include development of further solder joint attachment reliability modeling for array packages, including discrete arrays for a variety of use environments. Major processing changes are needed by fabricators to meet the new design requirements for component interposers. Use of plastic BGA packages continues to cause some problems. In addition to being moisture sensitive, the assembled package can have rework issues. Power cycling during field life effects moisture adsorption and its influence on field life. NASA research with electronic noses, System-in-a-Package or System-on-a-Chip Technologies, and the identification of manufacturing processes, materials, quality, and reliability of embedded passive interconnects required for extreme temperature applications will be discussed. Technology challenges and forecasts are also given.