Verilog RTL Model Based Concurrent Fault Simulation

摘要

The VLSI testing is being pushed to the high-level based technology. We proposed a Verilog Register transfer level Model (VRM) for integrated circuits. Based on the VRM, a RTL concurrent fault simulation approach is presented in this paper. After defining RTL fault models and super faults, the concurrent fault simulation algorithm is given. The corresponding RTL concurrent fault simulator VFSim was implemented. The initial experiments show that the RTL fault simulator is efficient for VLSI circuits.