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Wafer Dicing Using Dry Etching on Standard Tapes and Frames

机译:使用在标准胶带和框架上使用干蚀刻的晶片切割

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To meet the changing demands of consumer product form factors, there has been a steady shift to thinner and smaller semiconductor die, both of which increase the challenges for die singulation. The traditional approach of saw dicing is facing new limitations due to die damage and throughput. Compounding these issues is the finite width of saw blades, saw blade loading from clearing multiple materials, and orthogonal layout restrictions. Laser dicing has been introduced to address some of these issues, but faces other limitations such as damage from the heat affected zone, ablation residues, throughput, and material incompatibilities (changes in transparency and absorption in the street). In some cases, a combination of both saw and laser has been utilized to surmount some of the technical obstacles. The recently introduced approach of front-side plasma singulation circumvents many of the limitations of saws and lasers. The technology presented in this work uses standard dicing tape and frames, is through-wafer complete die separation, and does not involve a subsequent wafer thinning or die cleaving step. Our approach utilizes lithographically defined singulation lines with typical widths of 10-15μm, and delivers chip/crack-free edges with low-stress rounded corners. The parallel nature of this singulation method enables non-orthogonal and non-linear singulation streets allowing die layout and design flexibility not achievable by saws and/or lasers. As a consequence, plasma singulation produces increased good die per wafer through better wafer area utilization, lower die failure (reduced corner stress with rounded geometry), and flexibility in die placement near wafer edge on larger die. One of the unique advantages is that this technology can be implemented without addition of any new masking layers but instead the use of the existing passivation, metals and/or upper dielectrics as masks. Implementing this technology across a wide range of die applications such as power, memory, logic, imaging sensors, LEDs, and MEMS must address a diverse range of variables such as compatible materials, bond pads/bumps, and backmetal. For dies with backside metal, a non-etch based method to allow full die separation while the dies are still attached to tape has been demonstrated.
机译:为了满足消费者对产品的形状因子不断变化的需求,出现了一个稳定的转向更薄更小的半导体管芯,这两者增加管芯分割的挑战。锯切割的传统方法正面临着因损坏模具和吞吐量的新限制。除了这些问题是锯片,从结算多种材料锯片加载,以及正交布局限制的有限宽度。激光切割已经被引入来解决其中的一些问题,但面临其他限制,例如从热影响区的损伤,烧蚀残渣,吞吐量和材料不兼容(在街上的变化的透明度和吸收)。在某些情况下,都看到和激光的结合已被用来克服一些技术障碍。前侧等离子切割规避许多锯和激光器的局限性最近引入的方法。在这项工作中所呈现的技术使用标准切割带和帧,是贯穿晶片的完整管芯分离,并且不涉及随后的晶片减薄或冲模切割步骤。我们的方法利用光刻限定具有10-15μm典型宽度分割线,并用低应力圆角提供芯片/无裂纹的边缘。这种分割法的并行特性使得非正交和非直线分割街道允许模具布局和设计灵活性不受锯和/或激光器实现的。其结果是,等离子体切割产生通过更好的晶片面积利用率提高每个晶片的良好裸片,下模失败(具有圆形的几何结构减小拐角应力),和灵活性邻近晶片边缘管芯放置在较大的模具。其中一个独特的优点是,这种技术能够在不增加任何新的掩模层的,而是利用现有的钝化,金属和/或电介质上作为掩模来实现。实现该技术在广泛的应用中模头如电源,存储器,逻辑,成像传感器,LED和MEMS必须解决的变量不同范围诸如相容材料,接合焊盘/凸点,与背金属。用于与背面金属模具,非基于蚀刻方法,以允许满管芯分离而管芯仍然附着到磁带已被证明。

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