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Wafer Dicing Using Dry Etching on Standard Tapes and Frames

机译:使用在标准胶带和框架上使用干蚀刻的晶片切割

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To meet the changing demands of consumer product form factors, there has been a steady shift to thinner and smaller semiconductor die, both of which increase the challenges for die singulation. The traditional approach of saw dicing is facing new limitations due to die damage and throughput. Compounding these issues is the finite width of saw blades, saw blade loading from clearing multiple materials, and orthogonal layout restrictions. Laser dicing has been introduced to address some of these issues, but faces other limitations such as damage from the heat affected zone, ablation residues, throughput, and material incompatibilities (changes in transparency and absorption in the street). In some cases, a combination of both saw and laser has been utilized to surmount some of the technical obstacles. The recently introduced approach of front-side plasma singulation circumvents many of the limitations of saws and lasers. The technology presented in this work uses standard dicing tape and frames, is through-wafer complete die separation, and does not involve a subsequent wafer thinning or die cleaving step. Our approach utilizes lithographically defined singulation lines with typical widths of 10-15μm, and delivers chip/crack-free edges with low-stress rounded corners. The parallel nature of this singulation method enables non-orthogonal and non-linear singulation streets allowing die layout and design flexibility not achievable by saws and/or lasers. As a consequence, plasma singulation produces increased good die per wafer through better wafer area utilization, lower die failure (reduced corner stress with rounded geometry), and flexibility in die placement near wafer edge on larger die. One of the unique advantages is that this technology can be implemented without addition of any new masking layers but instead the use of the existing passivation, metals and/or upper dielectrics as masks. Implementing this technology across a wide range of die applications such as power, memory, logic, imaging sensors, LEDs, and MEMS must address a diverse range of variables such as compatible materials, bond pads/bumps, and backmetal. For dies with backside metal, a non-etch based method to allow full die separation while the dies are still attached to tape has been demonstrated.
机译:为满足消费产品形状因素的不断变化,较薄且较小的半导体管芯的稳定转变,这两者都增加了模具分割的挑战。由于模具损坏和吞吐量,传统的Saw Dicing方法面临新的限制。复合这些问题是锯片的有限宽度,锯片装载从清除多种材料,以及正交的布局限制。引入激光切割以解决其中一些问题,但面临其他限制,例如热影响区,消融残余物,产量和材料不相容性(街道透明度和吸收的变化)。在某些情况下,锯和激光的组合已经利用来超越一些技术障碍。最近引入的前侧等离子体分割方法,避免了锯和激光的许多局限性。本工作中提供的技术使用标准切割带和框架,是通过 - 晶片完成模具分离,并且不涉及随后的晶片变薄或模具切割步骤。我们的方法利用了典型宽度为10-15μm的光刻定义的分割线,并具有低应力圆角的芯片/裂缝边缘。该整理方法的并行性质使非正交和非线性分割街道能够通过锯和/或激光不能实现的模具布局和设计灵活性。因此,通过更好的晶片区域利用,降低模具故障(用圆形几何的减小的角应力),等离子体分割通过更好的晶圆面积利用,降低模具失败(减小的圆形几何),以及在较大的模具上附近晶片边缘附近的模具放置的灵活性。一个独特的优点之一是,可以在不添加任何新的掩模层的情况下实现该技术,而是使用现有钝化,金属和/或上部电介质作为掩模。在广泛的模具应用中实施此技术,例如电源,存储器,逻辑,成像传感器,LED和MEMS必须解决各种变量,例如兼容材料,粘接焊盘/凹凸和后级。对于具有背面金属的模具,基于非蚀刻的方法,以允许全芯片分离,同时仍然附着在胶带上。

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