Large Size Silicon Interposer and 3D IC Integration for System-in-Packaging (SiP)

摘要

The feasibility study of a 3D IC integration SiP is demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) passive interposer (28mm x 28mm) with double sided wiring layers. This interposer is used to support a very large chip (22mm x 18mm) on its top-side and 2 smaller chips (10mm x 10mm) at its bottom-side (a truly 3D IC integration). The bottom side of this interposer is attached to an organic substrate (40mm x 40mm) (with ordinary lead-free solder bumps). The lead-free micro solder bumps (Cu/Sn) on all the chips are made by wafer bumping with a UBM (under bump metallurgy) of Ti/Cu and the bump structure of Cu and Sn.